Do you have a synthesis challenge ?

posted Aug 26, 2010, 11:28 PM by Jay Singh   [ updated Aug 27, 2010, 12:02 AM ]
We are focused at solving RTL synthesis problems using methodology and tools.

We need your help to identify a RTL synthesis challenge. Whether it is because of design size, too many interconnects, timing problem, routability or run times. 

Let us know by email ( Synthesis Challenge ), if you have one. Mutual NDA is not a problem.