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Do you have a challenge ?

This news feed is dedicated to challenges in doing advanced designs. May be you have need to reduce design cycle time or improve quality. We are interested in knowing about your challenges.

Please help us, help you.

Do you have design cycle challenge ?

posted Aug 26, 2010, 11:37 PM by Jay Singh   [ updated Aug 27, 2010, 1:20 AM ]

We are focused at solving various design cycle timeline related challenges with the use of methodology, automation, rules and data management. 

We need your help to identify any problem that generally makes you slip your schedule. 

We believe design architecture is core of semi conductor companies. We are interested in  any challenges other than design architecture which makes it difficult to meet the dead lines. Whether it is because of lack of time, lack of expertise, number of things, size of design or verification challenges.

Please let us know by email ( Design Cycle Challenge ), if you have one. Mutual NDA is not a problem.

Do you have an advanced node challenge ?

posted Aug 26, 2010, 11:32 PM by Jay Singh   [ updated Aug 26, 2010, 11:59 PM ]

We are focused at solving problems specific to advanced nodes. Our special interest goes towards geometries 65nm and below. We have methodology and guidance to address most issues.

We need your help to identify any specific challenge you are facing on advanced technology nodes. Whether it is because of large number of parasitics, yield or on chip variations.

Let us know by email ( Technology Challenge ), if you have one. Mutual NDA is not a problem.

Do you have a flip-chip challenge ?

posted Aug 26, 2010, 11:31 PM by Jay Singh   [ updated Aug 27, 2010, 12:01 AM ]

We have gone through most of these challenges in bottom up, top down and combination of both. We are committed to simplify chip to package synchronization, bump inventory maintenance, bump routability and bump route quality analysis. There are methodology solutions and automation which could help 

We need your help to identify any flip-chip or packaging challenge that's becoming a hurdle in the way to producing  successful chips.

Let us know by email ( Flip Chip Challenge ), if you have one. Mutual NDA is not a problem.

Do you have a synthesis challenge ?

posted Aug 26, 2010, 11:28 PM by Jay Singh   [ updated Aug 27, 2010, 12:02 AM ]

We are focused at solving RTL synthesis problems using methodology and tools.

We need your help to identify a RTL synthesis challenge. Whether it is because of design size, too many interconnects, timing problem, routability or run times. 

Let us know by email ( Synthesis Challenge ), if you have one. Mutual NDA is not a problem.

Do you have a Simulation challenge ?

posted Aug 26, 2010, 11:18 PM by Jay Singh   [ updated Aug 27, 2010, 12:04 AM ]

We are focused at solving simulations problems using methodology, tools and innovation.

We need your help to identify a schematic or a post layout simulation challenge. Whether it is because of design size, too many parasitics at newer nodes or it's too many corners.

Let us know by email ( Simulation Challenge ), if you have one. Mutual NDA is not a problem.

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